The present invention relates to a fabrication method of a semiconductor device, and more particularly, to a method for fabricating a semiconductor device that prevents a plate from being punched during an etching for forming a metal interconnection.
In a DRAM device, a metal interconnection is disposed over a device for inputting or outputting an electrical signal to/from the device. The metal interconnection is configured with a first metal interconnection M1 or a multi-layered structure having first to third metal interconnections M1 to M3, whereby the electrical signal is inputted or outputted therethrough. A lowermost metal interconnection among the multi-layered metal interconnections is generally called ‘first metal interconnection M1’. The first metal interconnection M1 is connected to underlying components, e.g., particularly, a capacitor and a bit line, through a first metal contact M1C. Here, an etching process for forming the first metal contact M1C is called ‘M1C etching’, which is used for forming a deep contact hole. In general, the M1C etching process is performed to form a contact hole by etching upper portions of a plate and a bit line for supplying a power to the plate and the bit line, wherein the plate is disposed over a storage node.
FIG. 1 illustrates a cross-sectional view of a typical method for fabricating a semiconductor device. Landing plug contacts 13 are formed on a substrate 11 having a cell region and a peripheral region, wherein the landing plug contacts 13 are insulated from each other by virtue of a first inter-layer insulation layer 12. A second inter-layer insulation layer 14 is formed, and a bit line BL is formed on the second inter-layer insulation layer 14. The bit line BL is simultaneously formed in the cell region and the peripheral region, wherein the bit line BL is configured with a tungsten layer 15A and a bit line hard mask nitride layer 15B, which are stacked in sequence. After forming a third inter-layer insulation layer 16 over the bit line BL, a storage node contact 17 penetrating the third and second inter-layer insulation layers 16 and 14 are formed such that the storage node contact 17 is connected to the landing plug contact 13.
An etch barrier nitride layer 18 and a fourth inter-layer insulation layer 19 are formed on the third inter-layer insulation layer 16. The fourth inter-layer insulation layer 19 and the etch barrier nitride layer 18 are sequentially etched to expose a portion of the cell region where a storage of a capacitor will be formed. A storage node 20 connected to the storage node contact 17 is formed. A dielectric layer 21 and a plate 22 are sequentially formed on the storage node 20. The plate 22 is formed of a TiN layer and a polysilicon layer, which are stacked in sequence. A fifth inter-layer insulation layer 23 is formed over the plate 22, and thereafter an M1C etching is performed. At this time, the M1C etching is simultaneously performed on the cell and peripheral region to thereby form contact holes 24A and 24B exposing a surface of the plate 22 and a surface of the tungsten layer 15A of the bit line BL.
In the typical method for fabricating the semiconductor device, since the plate 22 is disposed over the storage node 20 and the bit line BL is disposed below the storage node contact under the storage node 20, a step height between the plate 22 and the bit line BL becomes too great, e.g., approximately 30,000 Å. Therefore, according to the typical method, when the M1C etching is simultaneously performed on the cell region and the peripheral region for etching the bit line BL, a conductive layer of the plate 22 cannot be resistant to the etching so that the conductive layer is punched therethrough (this is often called punch phenomenon).
FIG. 2 illustrates a micrograph showing a punch phenomenon of a plate according to the typical method. It is understood that there occurs a punch phenomenon of the plate when simultaneously performing the M1C etching on the bit line and the plate. The reason the punch phenomenon occurs is that there exists a great step height between the plate and the bit line. That is, since the polysilicon layer and the TiN layer as the conductive material for the plate have high etch selectivity with respect to an oxide layer, the etching rate is slow when the M1C etching is performed up to the top portion of the bit line. However, an etching time should be increased due to a great step height, which causes the plate to be punched.
Because the punch phenomenon does not have an effect on a device fabrication, following processes are still performed even after the plate is punched, in the typical method. However, as the device is miniaturized, a sidewall of the plate is partially oxidized if the plate is punched. Accordingly, a cleaning process cannot be performed well, which increases a contact resistance in depositing a barrier metal layer, i.e., a portion of a first metal interconnection M1. In the long run, a resistance of the plate is increased.
Thus, to avoid such a limitation, the contact holes over the plate and the bit line may be formed through respective etching processes. This leads to long process time and high fabrication cost. As another method to avoid the limitation, there has been proposed a method for increasing etch selectivity between the TiN layer and the polysilicon layer by changing plasma gas. This typical method, however, is difficult to overcome the above limitation due to a great step height between the plate and the bit line.